Transistors may be utilized in numerous applications; such as, for example, dynamic random-access memory (DRAM), resistive RAM (RRAM), magnetic RAM (MRAM), spin-transfer-torque-MRAM (STT-MRAM), etc.
A field-effect transistor (FET) comprises a gated channel region between a pair of source/drain regions.
A continuing goal of semiconductor fabrication is to increase the density of integration. It is therefore desired to develop improved FET architectures which are suitable for utilization in highly-integrated architectures, and to develop methods for fabricating such FET architectures.
Wafer bonding is a methodology which may have application relative to integrated assemblies. Wafer bonding comprises the bonding of two semiconductor assemblies to one another to form a composite structure. One method of wafer bonding comprises formation of silicon dioxide surfaces across each of the assemblies which are to be bonded to one another. The silicon dioxide surfaces are then placed against one another, and subjected to appropriate treatment to induce covalent bonding between the surfaces and thereby form the composite structure. The treatment utilized to induce the covalent bonding may be a thermal treatment. In some applications, such thermal treatment may utilize a temperature in excess of 800° C. Alternatively, one or both of the silicon dioxide surfaces may be subjected to a plasma treatment prior to the thermal treatment, and in such aspects the temperature of the thermal treatment may be reduced to a temperature within a range of from about 150° C. to about 200° C. The bonding of the silicon dioxide surfaces to one another may be referred to as “fusion bonding”.